In general, an image sensor is a semiconductor device for converting optical images into electric signals, and is mainly classified as a charge coupled device (CCD) or a CMOS image sensor.
The CCD has a plurality of photodiodes (PDs), which are arranged in the form of a matrix in order to convert optical signals into electric signals. The CCD includes a plurality of vertical charge coupled devices (VCCDs) provided between photodiodes and vertically arranged in the matrix so as to transmit electrical charges in the vertical direction when the electrical charges are generated from each photodiode. The CCD also includes a plurality of horizontal charge coupled devices (HCCDs) for transmitting the electrical charges that have been transmitted from the VCCDs in the horizontal direction, and a sense amplifier for outputting electric signals by sensing the electrical charges being transmitted in the horizontal direction.
However, the CCD has various disadvantages, such as a complicated drive mode and high power consumption. Also, the CCD requires multi-step photo processes, so the manufacturing process for the CCD is complicated.
In addition, since it is difficult to integrate a controller, a signal processor, and an analog/digital converter (A/D converter) onto a single chip of the CCD, the CCD is not suitable for compact-size products.
Recently, the CMOS image sensor is spotlighted as a next-generation image sensor capable of solving the problems of the CCD.
The CMOS image sensor is a device employing a switching mode to sequentially detect an output of each unit pixel by means of MOS transistors, in which the MOS transistors are formed on a semiconductor substrate corresponding to the unit pixels through a CMOS technology and using peripheral devices, such as a controller and a signal processor.
That is, the CMOS image sensor includes a photodiode and a MOS transistor in each unit pixel, and sequentially detects the electric signals of each unit pixel in a switching mode to realize images.
Since the CMOS image sensor makes use of CMOS technology, the CMOS image sensor has advantages such as low power consumption and a simple manufacturing process with a relatively smaller number of photo processing steps.
In addition, the CMOS image sensor allows the product to have a compact size, because the controller, the signal processor, and the A/D converter can be integrated onto a single chip.
Therefore, CMOS image sensors have been extensively used in various applications, such as digital still cameras and digital video cameras.
The CMOS image sensors are classified as 3T-type, 4T-type and 5T-type CMOS image sensors according to the number of transistors formed in a unit pixel. The 3T-type CMOS image sensor includes one photodiode and three transistors, and the 4T-type CMOS image sensor includes one photodiode and four transistors.
The layout for a conventional unit pixel of the 4T-type CMOS image sensor is as follows:
FIG. 1 is an equivalent circuit diagram illustrating a 4T-type CMOS image sensor according to a related art, and FIG. 2 is a layout view showing a unit pixel of the 4T-type CMOS image sensor according to the related art.
As shown in FIG. 1, a unit pixel 100 of the CMOS image sensor includes a photodiode 10, which is an optoelectronic device, and four transistors.
Here, the four transistors include a transfer transistor 20, a reset transistor 30, a drive transistor 40, and a select transistor 50. In addition, a load transistor 60 is electrically connected to an output terminal OUT of each unit pixel 100.
Reference characters FD, Tx, Rx, Dx, and Sx represent a floating diffusion area, the gate voltage of the transfer transistor 20, the gate voltage of the reset transistor 30, the gate voltage of the drive transistor, and the gate voltage of the select transistor, respectively.
As shown in FIG. 2, the unit pixel of the CMOS image sensor has an active area defined thereon and an isolation layer formed on a predetermined area of the unit pixel except for the active area. The photodiode PD is formed on a wider region of the active area, and gate electrodes 23, 33, 43 and 53 of the four transistors are formed overlapping the remaining regions of the active area.
The first gate electrode 23 corresponds to the transfer transistor 20, the second gate electrode 33 corresponds to the reset transistor 30, the third gate electrode 43 corresponds to the drive transistor 40, and the fourth gate electrode 53 corresponds to the select transistor 50.
Dopants are implanted into the active area of each transistor except for lower portions of the gate electrodes 23, 33, 43 and 53, so that source/drain (S/D) areas of the transistors are formed.
FIGS. 3A to 3E are sectional views taken along line I-I′ of FIG. 2 to illustrate the procedure for fabricating a CMOS image sensor according to the related art.
Referring to FIG. 3A, an epitaxial process is performed relative to a high-density P++ semiconductor substrate 61, thereby forming a low-density P− epitaxial layer 62.
Then, after defining an active area and an isolation area on the semiconductor substrate 61, an isolation layer 63 is formed on the isolation area through an STI (shallow trench isolation) process or a LOCOS process.
In addition, a gate insulating layer 64 and a conductive layer 65a (for example, a high-density multi-crystalline silicon layer) are sequentially deposited on the entire surface of the epitaxial layer 62 formed with the isolation layer 63.
Then, a first photoresist film 66 is coated on the conductive layer 65a, and then the first photoresist film 66 is patterned by an exposure and development process to define a gate area.
After that, referring to FIG. 3B, the conductive layer 65a and the gate insulating layer 64 are selectively removed using the patterned first photoresist film 66 as a mask, thereby forming a gate electrode 65.
Then, referring to FIG. 3C, the first photoresist film 66 is removed, and a second photoresist film 67 is coated on the entire surface of the semiconductor substrate 61 including the gate electrode. Then, the second photoresist film 67 is selectively patterned by an exposure and development process, to expose the photodiode area.
Then, low-density n-type dopants are implanted into the exposed photodiode area, thereby forming the low-density n-type diffusion area 68.
Here, the low-density n-type diffuision area 68 is deeply formed by using a high energy implant to improve the sensitivity of the image sensor.
The low-density n-type diffusion area 68 is a source area of the reset transistor Rx shown in FIGS. 1 and 2).
Then, referring to FIG. 3D, the second photoresist film 67 is completely removed, and a silicon nitride (SiN) layer is formed on the entire surface of the semiconductor substrate 61 including the gate electrode 65. An etch-back process is performed relative to the entire surface of the semiconductor substrate 61, to form insulating layer sidewalls 69 at both sides of the gate electrode 65.
Then, a third photoresist film 70 is coated on the entire surface of the semiconductor substrate 61, and selectively patterned by an exposure and development process to define a source/drain area.
Then, high-density n+ type dopants are implanted into the exposed source/drain area using the patterned third photoresist film 70 as a mask, thereby forming a high-density n+ type diffusion area 71.
Then, referring to FIG. 3E, the third photoresist film 70 is removed and a heat-treatment process (for example, a rapid thermal process) is performed with respect to the semiconductor substrate 61, thereby diffusing dopants in the n type diffusion area 68 and the n+ type diffusion area 71.
However, the conventional method of fabricating the CMOS image sensor has following problems.
When the gate is formed by the conventional CMOS fabrication process, damage is caused to the surface of the photodiode during the etching process for patterning the gate, thereby incurring dark current of the photodiode.
That is, when forming the gate electrode and the insulating layer sidewall, damage occurs on the surface of the semiconductor substrate. In addition, since the insulating layer sidewall is made from a silicon nitride layer, the surface of the semiconductor substrate is subject to stress due to silicon nitride, so that leakage current is generated, degrading the performance of the image sensor.